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| SL74HC4094 8-Bit Serial-Input Shift Register With Latched 3-State Outputs High-Performance Silicon-Gate CMOS The SL74HC4094 is identical in pinout to the LS/ALS4094. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. This device consists of an 8-bit shift register and 8-bit D-type latch with three-state parallel outputs. Data is shifted serially through the shift register on the positive going transition of the clock input signal. The output of the last stage SQH can be used to cascade several devices. Data on the SQH output is transferred to a second output (SQH') on the following negative transition of the clock input signal. The data of each stage of the shift register is provided with a latch, which latches data on the negative going transition of the Strobe input signal. When the Strobe input is held high, data propagates through the latch to a 3state output buffer. This buffer is enabled when Output Enable input is taken high. * Outputs Directly Interface to CMOS, NMOS, and TTL * Operating Voltage Range: 2.0 to 6.0 V * Low Input Current: 1.0 A * High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION SL74HC4094N Plastic SL74HC4094D SOIC TA = -55 to 125 C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs Clock Output Enable PIN 16 =VCC PIN 8 = GND L L H H H H NC = No Change Z = high impedance X = don't care System Logic Semiconductor Parallel Outputs Strobe X X L H H X A X X QA Z Z QN Z Z NC QN-1 QN-1 NC Serial Outputs SQH SQH' Q6 NC NC SQH Q6 Q6 Q6 NC NC NC X NC L H L H X NC NC SQH SLS SL74HC4094 MAXIMUM RATINGS * Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 20 25 50 750 500 -65 to +150 260 Unit V V V mA mA mA mW C C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA tr, t f Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min 2.0 0 -55 0 0 0 Max 6.0 VCC +125 1000 500 400 Unit V V C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. SLS System Logic Semiconductor SL74HC4094 DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) VCC Symbol Parameter Test Conditions V Guaranteed Limit 25 C to -55C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 0.1 0.5 85 C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 1.0 5.0 125 C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 1.0 10 A A V Unit VIH Minimum High-Level Input Voltage Maximum Low -Level Input Voltage Minimum High-Level Output Voltage VOUT= 0.1 V or VCC-0.1 V IOUT 20 A VOUT=0.1 V or VCC-0.1 V IOUT 20 A VIN=VIH or VIL IOUT 20 A VIN= VIH or VIL IOUT 4.0 mA IOUT 5.2 mA 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0 V VIL V VOH V VOL Maximum Low-Level Output Voltage VIN=VIH or VIL IOUT 20 A VIN= VIH or VIL IOUT 4.0 mA IOUT 5.2 mA IIN IOZ Maximum Input Leakage Current Maximum Three-State Leakage Current VIN=VCC or GND Output in High-Impedance State VIN= VIL or VIH VOUT=VCC or GND VIN=VCC or GND IOUT=0A ICC Maximum Quiescent Supply Current (per Package) 6.0 4.0 40 160 A SLS System Logic Semiconductor SL74HC4094 AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input t r=t f=6.0 ns) VCC Symbol fmax Parameter Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 5) Maximum Propagation Delay, Clock to SQH (Figures 1 and 5) Maximum Propagation Delay, Clock to QA-QH (Figures 2 and 5) Maximum Propagation Delay ,Output Enable to QA-QH (Figures 3 and 6) Maximu m Propagation Delay ,Output Enable to QA-QH (Figures 3 and 6) Maximum Input Capacitance Maximum Three-State Output Capacitance (Output in High-Impedance State), QA-QH Power Dissipation Capacitance (Per Package) CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Guaranteed Limit 25 C to -55C 6 30 35 150 30 26 195 40 33 125 25 21 175 35 30 10 15 85C 5 25 28 190 38 33 245 50 42 155 31 26 220 44 37 10 15 125C 4 20 23 225 45 38 295 60 50 190 38 32 265 53 45 10 15 Unit MHz tPLH, t PHL ns tPLH, t PHL ns tPLZ, t PHZ ns tPZL, t PZH ns CIN COUT pF pF Typical @25C,VCC=5.0 V 300 pF TIMING REQUIREMENTS(CL=50pF,Input t r=t f=6.0 ns) VCC Symbol tsu Parameter Minimum Setup Time, Serial Data Input A to Clock (Figure 4) Minimum Hold Time, Clock to Data Input A (Figure 4) Minimum Pulse Width, Strobe (Figure 1) Maximum Input Rise and Fall Times (Figure 1) V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Guaranteed Limit 25 C to -55C 50 10 9.0 3 3 3 80 16 14 1000 500 400 85C 65 13 11 3 3 3 100 20 17 1000 500 400 125C 75 15 13 3 3 3 120 24 20 1000 500 400 Unit ns th ns tw ns tr, t f ns SLS System Logic Semiconductor SL74HC4094 Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms Figure 4. Switching Waveforms Figure 5. Test Circuit Figure 6. Test Circuit SLS System Logic Semiconductor SL74HC4094 EXPANDED LOGIC DIAGRAM SLS System Logic Semiconductor SL74HC4094 TIMING DIAGRAM SLS System Logic Semiconductor |
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